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Sheet目录3878

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Micrel, Inc.

KSZ8841-PMQL

October 2007

M9999-100407-1.5

The ConfigParam in the EEPROM format is shown below.

Bit

Name

Description

NEW_CAP

New Capabilities

Indicates whether or not the KSZ8841-PMQL implements a list of new capabilities.

When set, this bit indicates the presence of New capabilities. When reset, New

capabilities are not implemented.

The value of this bit is loaded to the New_cap bit in CFCS register.

NO_SRST

No Soft Reset

When this bit is set, indicates that KSZ8841-PMQL transitioning from D3_hot to D0

because of PowerState commands do not perform an internal reset. Configuration

Context is preserved. Upon transition from the D3_hot to the D0 Initialized state,

no additional operating system intervention is required to preserve Configuration

Context beyond writing the PowerState bits.

When this bit is clear, KSZ8841-PMQL performs an internal reset upon

transitioning from D3_hot to D0 via software control of the PowerState bits.

Configuration Context is lost when performing the soft reset. Upon transition from

the D3_hot to the D0 state, full reinitialization sequence is needed to return the

device to D0 Initialized.

Regardless of this bit, devices that transition from D3_hot to D0 by a system or

bus segment reset will return to the device state D0 Uninitialized with only PME

context preserved if PME is supported and enabled.

This bit is loaded to bit 3 of CPMC register

Reserved

PME_D2

PME -Support D2

When this bit is set, the KSZ8841-PMQL asserts PME event when the KSZ8841-

PMQL is in D2 state and PME_EN is set. Otherwise, the KSZ8841-PMQL does not

assert PME event when the KSZ8841-PMQL is in D2 state.

This bit is loaded to bit 13 of PMCR register, and bit 29 of CCID register.

PME_D1

PME Support D1

When this bit is set, the K8841P asserts PME event when the K8841P is in D1

state and PME_EN is set. Otherwise, the KSZ8841-PMQL does not assert PME

event when the KSZ8841-PMQL is in D1 state.

This bit is loaded to bit 12 of PMCR register, and bit 28 of CCID register.

D2_SUP

D2 support

When this bit is set, the KSZ8841-PMQL supports D2 power state.

This bit is loaded to bit 10 of PMCR register, and bit 26 of CCID register.

D1_SUP

D1 support

When this bit is set, the KSZ8841-PMQL supports D1 power state.

This bit is loaded to bit 9 of PMCR register, and bit 25 of CCID register.

8 - 6

Reserved

DSI

Device Specific Initialization

This bit indicates whether special initialization of this function is required (beyond

the standard PCI configuration header) before the generic class device driver is

able to use it.

A “1” indicates that the function requires a device specific initialization sequence

following transition to the D0 uninitialized state. This bit is loaded to bit 5 of PMCR

Reserved

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